The present invention relates to calibrating circuits generally and, more particularly, to a method, architecture and circuit for selecting, calibrating and monitoring a plurality of circuits.
A conventional approach to calibrating circuits is to (i) calibrate a single buffer during chip power-up and (ii) program any remaining buffers to that calibrated value. An example of this approach is the xe2x80x9cProgrammable Output Impedance Circuitxe2x80x9d used by the 1302 PAQ SRAM chip, the data sheet of which is hereby incorporated by reference in its entirety.
Because the 1302 PAQ SRAM chip has output buffers located on opposite sides of the chip die, a single cycle calibration approach does not accurately account for process times of uncalibrated outputs located away from the calibrated output. As a result, the conventional calibration approach produces a mismatch in process times introducing an error of +/xe2x88x925% or more.
The present invention concerns a circuit comprising a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.
The objects, features and advantages of the present invention include providing a circuit that may (i) calibrate a plurality of circuits, (ii) monitor the calibration of a plurality of circuits and/or (iii) continuously monitor and calibrate a plurality of circuits.